To realize a high density memory device, for example of 128 Mbit, a possible approach includes assembling a plurality of memories (chips) of a certain size inside a single package, for example two memory chips of 64 Mbit each. The so obtained memory has a storage size equal to the sum of the sizes of the single memory chips. The advantage of this approach is that it is not necessary to re-design a new integrated device.
This approach is largely used by manufacturers of memory devices. For sake of simplicity, the assembling of a twin stacked memory is described. The so-called “twin stacked” memory is realized by assembling two memory chips or memories, generally identical, in a single package, bonding together the connection lines to the input/output pins of each memory in common on the array of input/output pins of the mounting frame of the package. According to known practice, the external enabling commands (commonly called chip enable or CE_N) are applied through distinct pins for commanding separately the two memories.
FIG. 1 depicts a classic structure of a “twin stacked” device. The bus of external addresses APD and DQPAD and the control signals OE_N, WE_N, RP_N are connected in common for constituting the equivalent array of input/output pins of the device. By contrast, the CE_N pins are multiple, that is each one is dedicated to a respective memory, and depending on the configuration of logic signals applied to them, four different combinations are possible, that may be selected by the user through dedicated external commands. The user may select one or the other of the two memories by lowering the respective logic “chip enable” command (CE), or place both memories in stand-by by forcing both “chip enable” commands to a high logic level.
There is a risk of both commands accidentally switching low, thus activating in parallel both memories. In any case, the system must manage a plurality of “chip enable” commands specific for the distinct memory chips contained in the packaged device.